1. Field of the Invention
The present invention relates to an auto precharge apparatus for a semiconductor memory device, and in particular to an improved auto precharge apparatus having an auto precharge gapless function protecting circuit, which can prevent a mis-operation of the semiconductor memory device.
2. Description of the Background Art
In general, a semiconductor memory device performs its operations according to an input command (for example, write/read command, precharge command, refresh command, etc.). Here, an illegal command can be inputted as the input command. The semiconductor memory device should not respond to the illegal command.
However, when a write/read command is inputted to the semiconductor memory device after an auto precharge operation, a chip is mis-operated due to absence of a circuit for protecting a gapless function.
A conventional auto precharge apparatus for a semiconductor memory device will be explained in detail with reference to FIGS. 1 and 2.
FIG. 1 is a block diagram illustrating the conventional autoprecharge apparatus, and FIG. 2 is a timing diagram of the major signals developed in the apparatus of FIG. 1.
Referring to FIG. 1, the conventional auto precharge apparatus includes a burst length counter 10, an auto precharge signal generator 20 and an internal row active signal generator 30.
The burst length counter 10 counts a burst length, calculates the number of data to be input/output, and transmits a burst end signal YBST_END. The auto precharge signal generator 20 confirms that an address  less than 10 greater than  is inputted in a high level when receiving the burst end signal YBST_END, and if the address  less than 10 greater than  is at a high level, it transmits an auto precharge command APCG. The internal row active signal generator 30 determines whether or not the row is active on the basis of the auto precharge signal APCG or a precharge signal PCG. That is, when receiving the precharge signal PCG, the internal row active signal generator 30 disables a word line, thereby performing precharge.
In FIG. 2, a second signal in which RAS transits to a low level is a row active signal ROWACT; a row active peri signal ROWACT_PE is activated and a main word line is enabled. Also, a third signal in which CAS transits to a low level is a read with auto precharge command. When burst length counting is ended and the address  less than 10 greater than  is at a high level, the row active peri signal ROWACT_PE is converted to a low level and the main word line is disabled at a high level.
The conventional auto precharge apparatus performs a write/read operation, and then automatically disables a word line after waiting for tDPL (data_in to precharge latency) although a precharge command is not inputted. If the tDPL time is not compensated, data are not fully written on a cell, which may generate a defect.
As illustrated in FIG. 2, a fourth low level signal of cas signal is a read with auto precharge command. However, since the row active peri signal ROWACT-PERI is active, data read is caused.
As stated above, while the auto precharge apparatus waits for the tDPL, if an illegal command is inputted to a bank, a new operation in accordance with the illegal command is executed in a state where the word line is not disabled, thereby causing a mis-operation.
Accordingly, it is a primary object of the present invention to prevent a mis-operation due to an illegal command externally inputted during an auto precharge operation, by separating a path for controlling a peri circuit unit from a path for controlling a core circuit unit.
Another object of the present invention is to prevent an externally-inputted illegal command from being executed by disabling a row active peri signal for controlling a peri circuit unit earlier than a row active core signal for controlling a core circuit unit during an auto precharge operation.
In order to achieve the above-described objects of the invention, there is provided an auto precharge apparatus having an auto precharge gapless function protecting circuit in a semiconductor memory device, including: an internal cas command signal generating means for receiving a bank address and an external cas command signal and generating an internal cas command signal; a burst length counter for receiving the internal cas command signal and a burst stop signal, and generating a burst end signal representative of an end of a burst operation; an auto precharge signal generating means for receiving the burst end signal, the internal cas command signal, an auto precharge end signal and an external address and generating an auto precharge peri signal and an auto precharge core signal; and an internal row active signal generating means for receiving the auto precharge peri signal, the auto precharge core signal, a precharge signal and an externally-inputted row active signal and generating a row active peri signal for enabling a word line and a row active core signal for disabling the word line. The internal cas command signal generating means receives the row active peri signal for enabling the word line and determines generation of the internal cas command signal.